In VLSI (Very Large Scale Integration) design, Clock Tree Synthesis (CTS) is a process used to distribute a clock signal to all the sequential elements (such as flip-flops) in a chip. During CTS, various rules are applied to ensure that the clock signal is distributed efficiently and with minimal skew.
One of the rules used in CTS is the Non-Default Rule (NDR). The NDR is a rule that allows the designer to specify a custom requirement for a particular clock path or net. This requirement could be related to timing, power, or other design constraints. The NDR is not enabled by default and must be explicitly specified by the designer.
When the CTS tool encounters an NDR, it modifies the clock tree synthesis process to meet the custom requirement specified by the designer. This can involve changing the shape or length of the clock tree or adjusting the placement of buffers to minimize clock skew.
The NDR is a powerful tool that allows designers to optimize their clock tree synthesis for specific requirements, but it also requires careful consideration to avoid introducing new problems or conflicts with other design rules.
In CTS, the designer specifies various design constraints such as maximum clock skew, maximum insertion delay, maximum power consumption, and so on. The CTS tool then generates a clock tree that meets these constraints. However, there may be cases where the designer wants to specify a custom requirement that is not covered by the default constraints.
This is where the NDR comes in. The NDR is a user-defined constraint that allows the designer to specify a custom requirement for a particular clock path or net. The designer can use the NDR to specify timing constraints, power constraints, or any other design requirement that is not covered by the default rules.
For example, suppose the designer wants to ensure that the clock signal reaches a particular flip-flop within a specific time window. In that case, the designer can specify an NDR that enforces this timing constraint. The CTS tool will then modify the clock tree to ensure that the timing constraint is met.
Practical Example analysis:
In semiconductor manufacturing, DRC is a process that checks whether the design of a chip meets the manufacturing rules and constraints. One of the common DRC rules is the width and space rule. The width and space rule specifies the minimum width and spacing between two adjacent metal or polysilicon lines or features.
For example, let's say that the manufacturing process specifies a minimum width of 0.1 microns and a minimum spacing of 0.2 microns between two adjacent metal lines. If the designer wants to specify a more stringent requirement, they can use the NDR to set a custom width and space rule.
Suppose the designer wants to specify a minimum width of 0.15 microns and a minimum spacing of 0.25 microns between two adjacent metal lines. They can define an NDR that overrides the default width and space rule for that specific metal layer. The NDR could look something like this:
In this example, the NDR specifies that the custom width and space rule should be applied only to the "metal1" layer. The minimum width and spacing are set to 0.15 and 0.25 microns, respectively.
The NDR allows the designer to set a custom requirement that is not covered by the default manufacturing rules. However, it is essential to ensure that the custom requirement does not conflict with other design rules or introduce new manufacturing problems. Therefore, designers must carefully evaluate the impact of an NDR on the overall design and manufacturing process before using it.