Efficient design implementation of any ASIC requires an appropriate style or planning approach that enhances the implementation cycle time and allows the design goals, such as area and performance, to be met.
There are two style alternatives for design implementation
- flat
- hierarchical
For small to medium ASICs, flattening the design is most suited; for very large and/or concurrent ASIC design, partitioning the design into sub-modules, or hierarchical style, is preferred.
The flat implementation style provides better area usage but requires effort during physical design and timing closure compared to the hierarchical style. This area advantage is mainly due to there being no need to reserve extra space around each sub-design partition for power, ground, and resources for the routing.
Timing analysis efficiencies arise from the fact that the entire design can be analyzed at once rather than analyzing each sub-circuit separately and then analyzing the assembled design later. The disadvantage of this method is that it requires a large memory space for data and run time increases rapidly with design size.
The hierarchical implementation style is mostly used for very large and/or con-current ASIC designs where there is a need for a substantial amount of computing capability for data processing. In addition, it is used when sub-circuits are designed individually.
However, hierarchical design implementation may degrade the performance of the final ASIC. This performance degradation is mainly because the components forming the critical path may reside in different partitions within the design, thereby extending the length of the critical path.
Therefore, when using a hierarchical design implementation style, one needs to assign the critical components to the same partition or generate proper timing constraints in order to keep the critical timing components close to each other, thereby minimizing the length of the critical path within the ASIC.