Synthesizable Verilog Code for the Gray Counter

In most of the practical applications binary and Gray counters need to be used. Gray counter output can be generated from the binary counter output by using the combinational logic. Refer Module x for the binary to Gray and Gray to binary code converters.

Gray counters are used in the multiple clock domain designs as only one bit changes on the active clock edge. Gray codes are used in the synchronizers. Gray counter is described in the below and in this only one bit is changing on the active clock edge with reference to the previous output of the counter.

In this active high reset input is ‘rst’. When ‘rst = 1’ then the output of counter ‘out’ is assigned to ‘0000’.

The counter described in this page is presettable counter and it has the synchronous active high ‘load_en’ input to sample the four-bit required presettable value. The data input is four bit and indicated as ‘data_in’. Counter has active high synchronous reset ‘rst’ input and when it is active high the status on output line ‘out’ is ‘0000’. During normal operation ‘rst’ is active low.

#Verilog Code:

`timescale 1ns / 1ps

//////////////////////////////////////////////////////////////////////////////////

// Company: VLSIVEDA

// Engineer: Vimal Mer

// 

// Create Date: 19.06.2023 12:31:12

// Design Name: Gray_Counter_Design

// Module Name: Gray_counter-Design

// Project Name: Sequential Circuits

// Target Devices: 

// Tool Versions: 

// Description:  Synchronous Reset, active high rest, counting in the Binary & convert to the Gray 

//////////////////////////////////////////////////////////////////////////////////

module Gray_counter_Design(out,data_in, clk, rst, load_en);

input [3:0]data_in;

input rst,clk, load_en;

output reg[3:0] out;

reg [3:0]count;

reg [2:0]q;

always @ (posedge clk)

begin 

if (rst)

begin 

count <= 4'b0;

{q[2],q[1],q[0]} <=3'b000;

out <= 4'b0;

end 

else if (load_en) //for preset the input for counting

begin

count <= data_in;

{q[2],q[1],q[0]} <= {data_in[2], data_in[1], data_in[0]};

out <= {data_in[3],data_in[2], data_in[1], data_in[0]};

end

else 

begin

count = count + 1'b1;

q[2] <= count[3]^count[2]; //for converting the binary to the Gray code

q[1] <= count[2]^count[1];

q[0] <= count[1]^count[0];

out <= {count[3], q[2], q[1], q[0]};

end

end

endmodule

Schematics:

Waveforms:

according to the schematics, when reset signal is on than Out, Count and Q[2:0] all are set to 0.

When Reset signal is off & Load_en becomes ON, then whatever the data_in is there it will be transferred to the count variable as well as the out variable. data_in[2] to data_in[0] is transferred to the register q[2:0]. Now it will load the preset data to count from that particular data. Now let when both are untrue than Count variable increment at each posedge of clock, sequentially register q2 to q0 will store the by doing the XOR of count[3] to count[0]. likewise xor of count[3] & count[2] into the q[2], xor of count[2] &count[1] into the q[1], xor of count[1]& count[0] into q[0]. Now the count[3], q[2], q[1] and q[0] into the out register for output, which is in term of the Gray code. 

By just making counter in the binary design and converting it into the gray code, it is possible to design the gray adder.

Thank you 

References:

Vaibbhav Taraate Digital Logic Design Using Verilog.