Working with Yosys open synthesis tool

Outlines : 

Download Yosys Synthesis tool

How to install Yosys open synthesis tool open below given link for download yosys.

Step 1 : Make Verilog file " fa.v " add this code inside this file.

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module fa(input a,b,c output sum,cout );

assign sum = (a ^ b ^ c );

assign cout = (a & b ) | (b & c) | (a & c);

endmodule

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Step 2 : make file with name yosys_script.ys

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# read design 

read_verilog fa.v 

#hierarchy -check -top fa

#the high-level stuff 

#proc; opt; fsm; opt; memory; opt

# mapping to internal cell library 

#techmap; opt

synth -top fa

# mapping flip-flops to mycells.lib 

#dfflibmap -liberty sky130_fd_sc_hd__tt_025C_1v80.lib

# mapping logic to mycells.lib 

abc -liberty sky130_fd_sc_hd__tt_025C_1v80.lib

# cleanup 

clean

#area info

tee -o chiparea.txt stat -liberty sky130_fd_sc_hd__tt_025C_1v80.lib

# write synthesized design 

write_verilog -noattr netlist.v

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Step 3 : open yosys by just type on terminal " yosys " 

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Step 4 : Now type " script yosys_script.ys " to run the this script to perform synthesis

yosys> script yosys_scipt.ys

After performing this script synthesis is done and and two files get generate 

1. chipare.txt

2. netlist.v